In a traditional master-slave flip-flop, the master and slave latches are transparent on complementary clock states. For example the master latch may be configured to be transparent (and thus able to latch the incoming data) when the clock is high. The master is then closed when the clock is low. Similarly, the slave latch may be configured to be transparent when the clock is low and closed when the clock is high. Alternatively, the master latch may be configured to transparent when the clock is low whereas the slave latch would then be transparent when the clock is high. In one clock cycle, the master latch thus captures the data on a first clock edge that is then latched by the slave latch in a subsequent second clock edge in the same clocking period. In a serial chain of such flip-flops, the data output from a slave latch in one flip-flop is the data input to the master latch in a subsequent flip-flop. A data bit latched in one flip-flop during a first clock cycle is thus latched in a subsequent flip-flop in a subsequent second clock cycle.
During relatively low-speed operation, the transfer from one flip-flop to a subsequent flip-flop is relatively straightforward as the relatively slow clocking speed provides ample setup timing margins in the timing path coupling the flip-flops. But in a high-speed design, the increased clocking speed makes it difficult for the subsequent flip-flop to capture its data at the clock-triggering edge because the setup time of the flip-flop together with the data propagation delay in the timing path between the flip-flops may approach or exceed the clock cycle period. Moreover, clock jitter reduces the effective time available in the clock cycle for data propagation and setup time. If the jitter, data propagation delay, and setup time together are longer than the clock cycle, the incoming data value will not be properly captured by the subsequent flip-flop. This erroneous operation is denoted as a setup timing failure.
To provide more robust high-speed performance despite clock jitter, it is thus known to provide a flip-flop in which the clocking of the master latch is delayed with respect to the clocking of the slave latch. The delayed clock to the master latch provides sufficient setup margin despite the existence of clock jitter such that the resulting flip-flop may be designated as “jitter-tolerant” (JT) flip-flop. Alternatively, the flip-flop may be denoted as a “soft-edge” flip-flop because the clock edge for the master has been delayed (softened) with regard to the arrival of the data. Without the delayed clock, a setup violation occurs if the data arrives after the clock edge due to jitter. But the delayed clock edge is thus softened with regard to such an early arrival of the data. As a result, setup margin (the required minimum amount of setup time) for the JT flip-flop may be reduced although this comes at the cost of an increased hold margin (the required minimum amount of hold time).
In contrast to a traditional master-slave flip-flop, sense-amplifier-based flip-flops are not amenable to soft-edge techniques because the slave latch is an asynchronous set-reset (SR) latch. The sense amplifier within a master latch for a sense-amplifier-based flip-flop includes a differential pair of transistors that respond to a data input signal and its complement by developing a differential voltage across their drain terminals. The sense amplifier also includes a pair of cross-coupled inverters that function with positive feedback to amplify the difference between the drain voltages for the differential pair such that an output voltage for each of the cross-coupled inverters quickly develops rail-to-rail (to the power supply voltage or to ground). The inverter output voltages form the set and reset signal for the asynchronous SR slave latch. Although a sense-amplifier-based flip-flop is thus advantageously faster than traditional master-slave flip-flops, delaying the clocking of the master-latch provides no benefit due to the asynchronicity of the slave latch.
There is thus a need in the art for jitter-tolerant sense-amplifier-based flip-flops.